VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.

Advantages of VHDL

The key advantage of VHDL, when used in system design, is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires). Another benefit is that VHDL allows the description of a concurrent system. VHDL is a dataflow language, unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time. A VHDL project is multipurpose. Being created once, a calculation block can be used in many other projects. However, many formational and functional block parameters can be tuned (capacity parameters, memory size, element base, block composition and interconnection structure). A VHDL project is portable. Being created for one element base, a computing device project can be ported on another element base, for example VLSI with various technologies.

Source: Wikipedia

About VHDL Training Course :

This course covers the VHDL Programming Concepts to design and Implementation of VHDL Programs on Xilinx Software and ModelSim Simulation and also run on Xilinx Spartan-3 BASYS2 and Xilinx Spartan 3E Boards.

Course Description

	·	Need, Scope and Use of VLSI
	·	Hardware description languages.
	·	Scope and History of VHDL
	·	Applications and Special features of VHDL
	·	Introduction to VHDL
		o	Design Process, Design Simulation and Design Synthesis
		o	Design Methodology- Top Down and Bottom Up
	·	Basics of VHDL
		o	Data objects, Classes and data types,
		o	Operators- Arithmetic , Relational and Logical
		o	Operator Overloading
		o	Types of delays
		o	Entity and Architecture declaration.

	·	Data Flow Model
		o	Using Concurrent Statements
	·	Behavioral Model
		o	Using Process Keyword, Conditional Statements  and Loops
	·	Structural Model
		o	Using Interconnection of Components

	·	Concurrent statements,
	·	Sequential statements,
	·	Array and loops,
	·	Resolution functions,
	·	Packages & Libraries,

	·	Design of Gates
		o	Design of AND gate
		o	Design of OR gate
		o	Design of NOT gate
		o	Design of UNIVERSAL gates
	·	Design of XOR and XNOR gate using other basic gates
	·	Design of 2:1 MUX using other basic gates
	·	Design of 1:4 Decoder
	·	Design of Half-Adder, Full Adder, Half Subtractor, Full Subtractor
	·	Design of 3:8 Decoder
	·	Design of 8:3 Priority Encoder
	·	Design of 4 Bit Binary to Gray code Converter
	·	Design of BCD to Excess3 code Converter
	·	Design of 4 Bit Binary to Seven Segment Display
	·	Design of 4 Bit Binary to BCD Converter using sequential statement
	·	Design an 8 Bit parity generator ( with for loop and Generic statements)
	·	Design of 2’s Complement for 8-bit Binary number

	·	Design of all types of Flip-Flops using ( if-then-else) Sequential Constructs
	·	Design of 8-Bit Shift Register with shift Right, Shift Left, Load and Synchronous reset.
	·	Design of shift Registers-
		o	SISO
		o	PIPO
		o	SIPO
		o	PISO
	·	Design of Synchronous 8-Bit universal shift register ( parallel-in, parallel-out).
	·	Design of Synchronous 8-bit Johnson Counter
	·	Design of Ring Counter
	·	Design
		o	Mod 3 Counter
		o	Mod 5 Counter
		o	Mod 7 Counter
		o	Mod 8 Counter
		o	Mod 16 counter
	·	Design a decimal up/down counter that counts up from 00 to 99 or down from 99 to 00.
	·	Design 3-line to 8-line decoder with address latch
	·	Design of ALU

	·	Moore machine
	·	Mealy machine


	·	Programmable logic devices (PLDs)
		o	ROM,
		o	PLA,
		o	PAL
	·	Complex PLD (CPLD)
	·	Field Programmable Gate Array (FPGA)
	·	Design and implementation using CPLDs and FPGAs

	1.	Introduction
	2.	FPGA and their types
	3.	Overview of the Digilent S3 board
	4.	Development flow
	5.	Overview of the Xilinx ISE project navigator
	6.	Tutorial on ISE project navigator
	7.	Tutorial on the ModelSim HDL simulator
	8.	General FPGA device
	9.	Overview of the Xilinx Spartan-3 devices
	10.	Create the Design project and HDL codes
	11.	Create a  Testbench and perform the RTL simulation
	12.	Constaints File and Need of Constaints File in VHDL
		Add a constraint file and synthesize and implement the code
	13.	Creating bit file for  Digilent S3 board
	14.	Using  iMPACT and Digilent Adept Software.
	15.	Programming/Loading Files to Target.

Hardware Interfacing:
	1.	Understanding Schematic of  Digilent S3 board	
	2.	Interfacing SRAM Memory Technique.
	3.	Interfacing LED with FPGA
	4.	Interfacing  SW  with FPGA
	5.	Interfacing 7-SEGMENT with FPGA	
	6.	UART Serial Communication with FPGA
	7.	PS2 Keyboard, PS2 Mouse
	8.	VGA (CRT) Controller Graphic and Text

* During training a project will be completed. Project expense will be beared by trainee.


Registration procedure for Imbuent training program is quite simple. We have online facility for registration of course. Please go through following steps for course registration…

  • Select Course
  • Download Registration form from Imbuent site Click Here to download form
  • Make a DD (Demand Draft) equal to the amount of course fees (DD Should be in the name of “Imbuent Technologies Pvt. Ltd.” and payable at “LUDHIANA”)
  • Fill the online registration form Click Here to fill online registration form
  • You will receive an confirmation email from us soon with a valid registration number
  • Send us DD, with Training Form, which you can download from our website

In case of any difficulty please feel free to contact us.